Job Description : Front end ASIC Design/ RTL Design & verification. Proficiency in Verilog/ Vera/ Specman. Exposure to C/ C++ is an advantage. Must have developed test benches / verification modules/ full chip. Candidate Profile : 4-8 years of experience in above mentioned technologies BE/B Tech/M.Tech degree in Electronics Engg./Comp Sc. Compensation and Benefits : Best Salary in the industry with benefits and travel allowances Oppurtunity to work with latest technologies Live and work the way you want to. |